Current-mode Multiple-valued Logic Research Articles

A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme

A multiple-valued data transfer scheme using X-net is proposed to realize a compact bit-serial reconfigurable VLSI (BS-RVLSI). In the multiple-valued data transfer scheme using X-net, two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each “X” intersection. One cell composed of a logic block and a switch block is connected to four adjacent cross points by four onebit switches so that the complexity of the switch block is reduced to 50% in comparison with the cell of a BS-RVLSI using an eight nearest-neighbor mesh network (8-NNM). In the logic block, threshold logic circuits are used to perform threshold operations, and then their binary dual-rail voltage outputs enter a binary logic module which can be programmed to realize an arbitrary two-variable binary function or a bit-serial adder. As a result, the configuration memory count and transistor count of the proposed multiplevalued cell are reduced to 34% and 58%, respectively, in comparison with those of an equivalent CMOS cell. Moreover, its power consumption for an arbitrary 2-variable binary function becomes 67% at 800MHz under the condition of the same delay time. key words: multiple-valued data transfer scheme, X-net, multiple-valued current-mode logic, MOS current-mode logic, fine-grain reconfigurable VLSI

CURRENT MODE CMOS QUATERNARY LOGIC FULL-ADDER

This paper proposes a quaternary-to-binary logic decoder, a quaternary current buffer, and a quaternary full-adder using current-mode multiple-valued logic (MVL) CMOS circuits. The proposed full-adder is superior to the previous MVL CMOS circuit in both the circuit occupied area and the performance. Comparing with the binary logic full-adder, the proposed full-adder is superior in the circuit occupied area. However, the circuit performance is inferior to the binary logic full-adder. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 μm standard CMOS technology with the supply voltage 2.5 V.

Low Static Powered Asynchronous Data Transfer for GALS System

For a globally asynchronous locally synchronous (GALS) system, data transfer mechanisms based on a current-mode multiple valued logic (CMMVL) has been studied to reduce complexity and power dissipation of wires. However, these schemes consume considerable amount of power even in idle states because of the static power caused by their inherent structure. In this paper, new encoder and decoder circuits using CMMVL are suggested to reduce the static power. The effectiveness of the proposed data transfer is validated by comparisons with the previous CMMVL scheme and conventional voltage-mode schemes such as dual-rail and 1-of-4 encodings through simulation with a 0.25-μm CMOS technology. Simulation results demonstrate that the proposed CMMVL scheme significantly reduces power consumption of the previous one and is superior to dual-rail and 1-of-4 schemes over wire length of 2 mm and 4 mm, respectively.

Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism

Conventional delay-insensitive (DI) data encodings require 2N+1 wires for transferring N-bit. To reduce complexity and power dissipation of wires in designing a large scaled chip, a DI data transfer mechanism based on current-mode multiple valued logic (CMMVL), where N-bit data transfer can be performed with only N+1 wires, is proposed. The effectiveness of the proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings through simulation at the 0.25-μm CMOS technology. Simulation results with wire lengths of 4mm or larger demonstrate that the CMMVL scheme significantly reduces delay-power product values of the dual-rail encoding with data rate of 5MHz or more and the 1-of-4 encoding with data rate of 18MHz or more.

Design of an area-efficient CMOS multiple-valued current comparator circuit

In the present state-of-the-art VLSI technology, the need for developing customised circuits to suit varying operating environments and specifications is escalating. The authors introduce an area-efficient current-mode comparator, which is based on modifications of the conventional CMOS current comparator. It has been verified by circuit simulations using the 0.25 /spl mu/m, 0.18 /spl mu/m, and 0.13 /spl mu/m CMOS technology from Chartered Semiconductor Manufacturing Pte. Ltd (CHRT ) that the proposed design acts as a perfect complement to the conventional current comparator for low threshold current (I/sub th/) levels. A low I/sub th/ is generally more favourable than a higher I/sub th/ as it tends to dissipate low static power. A more assuring and promising fact is that the area advantage becomes more significant with reducing feature size/technology. This attribute blends well with the contemporary and ongoing process technology miniaturisation. Together with the conventional and recently reported current comparator designs, the proposed current comparator has been integrated into a positive-digit adder (PDA) using the current-mode multiple-valued logic (CMMVL) approach with 1.8 V/0.18 /spl mu/m CMOS technology. The PDA utilising the new current comparator occupies a silicon area of only 40.2 /spl mu/m/sup 2/, which is only 77.2% and 22.6% of those of the conventional and contemporary circuits, with a power-delay product improvement of 7.3% and 70.4%, respectively.

Redundant arithmetic, algorithms and implementations

Performance in many very-large-scale-integrated (VLSI) systems such as digital signal processing (DSP) chips, is predominantly determined by the speed of arithmetic modules like adders and multipliers. Even though redundant arithmetic algorithms produce significant improvements in performance through the elimination of carry propagation, efficient circuit implementations of these algorithms have been traditionally difficult to obtain. This work presents a survey of circuit implementations of redundant arithmetic algorithms. The described implementations are divided into three main groups: (1) conventional binary logic circuits, which encode the multivalued digits of redundant arithmetic into two or more binary digital signals; (2) current-mode multiple-valued logic circuits, which directly represent multivalued redundant digits using non-binary digital current signals; and (3) heterostructure and quantum electronic circuits, intended for very compact designs capable of operating at extremely high speeds. For each of the circuits, the operating principle is described and the main advantages and disadvantages of the approach are discussed and compared.

A CMOS latch circuit for multiple-valued bi-directional current signals

Abstract A new latch circuit for bi-directional multiple-valued logic (MVL) current signals has been realized in a standard 2-microri poly-silicon gate CMOS process. The circuit accepts and quantizes a bi-directional input current during the SETUP clock phase and latches the quantized input during the HOLD clock phase. Using logical current increments of only l0μA, the bi-directional current-mode MVL latch set-up and hold time has been determined to total approximately 45 ns. The input/output propagation delay for transitions between adjacent states has been determined to be approximately 45 ns at these low current levels.